The Watchtower Brief — Industry signals shaping the future of semiconductor design.
For much of the past two decades, High-Level Synthesis (HLS) has occupied an unusual position in semiconductor design. Everyone knew the idea was powerful. Many teams experimented with it. A few organizations adopted it successfully. But a large portion of the industry continued building chips the same way it always had: starting from RTL and refining the design until it met its performance, power, and area targets. For a long time, that approach worked well enough. But the design environment surrounding modern silicon programs has changed dramatically. Those changes are forcing many engineering leaders to revisit a question that once felt optional:
Should we finally introduce higher abstraction into the design flow?
Modern chip programs look very different from those of even a decade ago. AI accelerators, networking pipelines, video processing, and data-centric compute blocks all share a common characteristic: they involve significant structured data movement and algorithmic processing. Designing these systems increasingly requires teams to explore architectural tradeoffs before RTL is fully stabilized. Memory hierarchies change. Pipeline structures evolve. Dataflow assumptions get revisited. Power constraints shift as new workloads emerge. In other words, the most important work often happens before the final RTL architecture is locked. And that is exactly where traditional flows begin to feel constrained.
RTL remains the foundation of silicon implementation, and for good reason. It provides precise control over the design's structure and integrates seamlessly with the downstream synthesis and verification ecosystem. But when teams rely exclusively on RTL for architectural exploration, they encounter a familiar problem: iteration speed. Evaluating a design idea often requires substantial code changes, new synthesis runs, and multiple refinement cycles. That process works, but it can make broad exploration expensive. As modern programs grow more complex, many engineering leaders are discovering that the limiting factor is not the creativity of their architects. It is the time required to evaluate each architectural decision.
This is where higher abstraction becomes valuable. HLS allows designers to express functionality closer to algorithmic intent and generate RTL implementations. That shift can dramatically accelerate early exploration by allowing teams to iterate on architecture before the final microarchitecture is frozen. Instead of asking:
“What does the RTL structure look like?”
teams can first ask:
“What architecture actually solves the problem?”
When used effectively, HLS becomes less about replacing RTL and more about expanding the design space engineers can realistically explore. And in modern silicon programs, that expanded design space is often where the biggest performance and efficiency gains are found.
If the benefits are clear, why did so many teams remain cautious? Historically, early HLS deployments introduced new challenges of their own. Some organizations found that:
• The generated RTL did not always correlate well with downstream synthesis results.
• Engineers needed specialized expertise to guide the tool effectively.
• Iteration loops could still be slower than expected.
• Adoption sometimes remained confined to a small group of specialists.
These experiences led many companies to conclude that HLS could work—but only in specific contexts. As a result, large parts of the industry continued relying primarily on traditional RTL methodologies.
Today, several factors are pushing engineering teams to revisit the question. First, architectural exploration has become more central to performance gains than ever before. Second, design schedules are tightening even as workloads grow more complex. Third, organizations increasingly need design methodologies that allow larger engineering teams to collaborate effectively across different abstraction layers. Taken together, these pressures are shifting how teams evaluate design tools and flows. The question is no longer simply whether HLS can generate correct RTL. The more relevant question has become:
Does higher abstraction help engineering teams reach better architectural decisions faster?
This is where the HLS ecosystem itself is evolving. Newer approaches aim to improve correlation with downstream synthesis, reduce the amount of manual tuning required, and make it easier for traditional RTL engineers to participate in higher-level design flows. In other words, the goal is no longer just to prove that abstraction works. It is to make abstraction practical at scale.
Rise Design Automation is one example of this new generation. The company focuses on faster iteration cycles, closer alignment with downstream synthesis results, and support for SystemVerilog-centric workflows that allow RTL designers to work more naturally within higher-level environments. For teams considering HLS for the first time, this approach can make the evaluation process significantly simpler. Instead of debating methodology in the abstract, engineering teams can simply compare the results of a real design block using different flows.
A subtle shift is underway across the semiconductor industry. For many years, the question surrounding HLS was:
“Does this approach really work?”
Today, the more relevant question may be:
“Are we leaving architectural opportunity on the table by staying entirely in RTL?”
The first wave of HLS adoption demonstrated that higher abstraction could deliver real benefits for certain classes of designs. The next wave will likely be driven by something simpler: the growing need to explore more architectural options in less time. As silicon programs continue to grow in complexity, engineering teams may discover that the most important advantage of HLS is not that it replaces RTL. It is that it allows designers to reach the right RTL architecture faster.
And that shift—from implementation-centric design to architecture-centric exploration—may ultimately determine how the next generation of chips is built.