AVESTRA · 5-MINUTE TECHNICAL WALKTHROUGH
A frontier LLM writes SystemVerilog Assertions that look right, compile cleanly and still check the wrong thing. Ashok Mehta shows three real cases and how Avestra’s 14-agent pipeline catches each one.
The invented signal. An assertion on a port that isn’t in the RTL, and how grounding every signal in the parsed source stops it.
The width-promotion trap. A FIFO assertion broken by a SystemVerilog sizing rule, with the RTL perfectly correct.
The false pass. A one-hot state register silently truncated, so the assertions check the wrong thing and report success.
The architecture. How agents analyze, reconcile, generate and cross-check before any output is final.
PRESENTED BY ASHOK MEHTA, FOUNDER, AVESTRA
Tell us who you are and the video opens right here.
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AiT is Avestra’s sales-representation partner. We’ll use your details to follow up about Avestra and won’t share them outside AiT and Avestra.
Why a Generic LLM Isn’t Enough for Assertions, with the code for all three cases.
If there’s interest in a closer look at Avestra on your designs, email Simon Bennett and we’ll set up a session with Ashok.