The interconnect fabric that stops waiting for the clock.
TimeWarp, Wormhole, and Retis are three interconnect IPs built on one clockless foundation — carrying data across long die routes, through the NoC, and across 3D die boundaries without a shared clock edge to wait on.
CACHE
PHY
Modern SoCs are outgrowing the wires that connect them.
As more function lands on a single die, the blocks that need to talk to each other keep drifting further apart. A memory controller sitting between the system cache and the DDR PHY can face a 15mm hop or more — and every trick designers have used to cover that distance, buffering, pipelining, careful routing, trades away latency to do it. Push a source-synchronous link far enough and clock degradation caps it below 1.5GHz, no matter how carefully it's floorplanned.
Generative AI didn't create the long-wire problem, but it raised the stakes. Workloads now carry latency budgets tight enough that the old trade-offs stop being trades and start being ceilings.
AI silicon hit the reticle limit before it hit its performance ceiling.
LLM parameter counts scaled roughly 410× between 2018 and 2022 (Gholami et al., UC Berkeley) — growth no single reticle can hold. The industry's answer has been chiplets, 2.5D interposers, and 3D die stacking, and that move buys area. But it also moves the long-wire problem from inside one die to across many: the interconnect now has to survive silicon interposers and hybrid-bond stacks without giving back the latency and power budget the workload can't spare.
It's the same pressure behind Chronos's own framing: shattering the memory wall means the interconnect can no longer be the thing standing still while everything else scales.
One clockless foundation, three IPs
TimeWarp, Wormhole, and Retis are all built on Chronos's proprietary clockless foundation, so they interoperate without a shared clock domain to synchronize against — data moves freely across long die routes, through the NoC, and across 3D boundaries without ever waiting on a clock edge.
TimeWarp™
Carries signals across long die routes with throughput that holds steady regardless of distance — so placement stops being a trade-off between system-cache latency and DDR-PHY latency. Deploys through the standard digital flow, no proprietary tools required.
Wormhole™
Purpose-built for die-to-die interconnect across hybrid-bonded stacks. Correct by construction, with pre- and post-bond die-level test built in — no clock ever has to travel across the bond.
Retis™
A high-performance, on-chip fabric for accelerator and AI SoC designs — built so throughput scales with the array, not with a clock tree.
Soft IP (TimeWarp) and hard macro (Wormhole, Retis), integrated through the standard digital flow. Automated netlist and constraint generation — no new toolchain, no clock-tree closure.
Sangiovese test-chip benchmarking (Chronos-reported): >115% throughput, >60% latency, and >85% bus-width reduction over a source-synchronous baseline.
SoC-protocol agnostic across ARM (AXI/CHI) and RISC-V, automotive-friendly, and complementary to UCIe on the long-reach die-to-die hop.
The physical layer EDA 3.0 has been missing.
Every layer of the EDA 3.0 lifecycle, from intent through yield, assumes a signal arrives when the design says it will. Chronos is what makes that assumption true at the physical layer — the substrate the rest of the stack is built on, not another layer within it.
Chronos just joined the AiT portfolio.
We're helping bring TimeWarp, Wormhole, and Retis to the accounts already feeling the long-wire penalty — the ones scaling past the reticle limit and finding out the clock is the bottleneck.