Want the easy way in? Drop us a line at ashley@ai-techsales.com and we'll book you into the right meeting — or use the links below.
Come talk silicon with us at DAC 2026.
We're bringing the full EDA 3.0 stack to Long Beach — twelve partners across architecture, verification, yield and orchestration. Catch Simon's EDA 3.0 overview, book a 1:1 briefing, or grab time with the partner that fits your roadmap.
Not at DAC, or need a time outside show hours? We'll meet on Microsoft Teams — grab a video briefing →
Monday night at DAC
🍺 Client Reception
Beer & and Wine on the patio — casual, walk-around networking. Not a sit-down dinner.
Can't get time at the booth? This is a great place to catch up instead.
Why spend 30 minutes with us
One stack, the whole lifecycle.
Most EDA tools make a single step faster. EDA 3.0 connects them — intent, architecture, RTL, verification, yield and orchestration as one AI-native lifecycle. We curate the partners that make that real, and at DAC you can see the whole stack in one place.
the opportunity EDA 3.0 is built for.
Reserved sessions · DAC only · limited seats
The EDA 3.0 Overview, live with Simon Bennett.
A 30-minute walk through the six-layer, AI-native semiconductor lifecycle — from intent to yield — and where the orchestration layer is still wide open. Held at reserved times across the show, Jul 26–29, at our base camp — Seaside Room S-3B, Long Beach Convention Center. Seats are capped so each session stays a conversation, not a keynote. Pick a time and register below.
Chief Strategy Officer & Co-Founder
Book a session
Pick your way in.
We'll meet at our base camp on the show floor — Seaside Room S-3B, Long Beach Convention Center — during DAC show hours, Sunday through midday Wednesday. After noon Wednesday we move to Teams.
Now pick the session you're interested in — browse by problem or by partner below, then choose a time.
Tell us what's slowing your roadmap and we'll bring the right partners to the table. Open any one to see who solves it — then sign up for a session.
L1 From intent to silicon Are your requirements drifting from your design?
Requirements live in one tool, the design in another, and traceability breaks the moment something changes — which is fatal when functional safety and audits are on the line. We connect requirements to the design record so intent survives all the way to tape-out.
L2 Architecture & pre-silicon Still waiting on silicon before your software can start?
Hand-tuned RTL and late software bring-up are where schedules go to die. AI-driven high-level synthesis and high-performance virtual prototypes let you explore architecture and boot real software before the chip exists.
L3 Design, IP & edge Is chiplet, IP, or edge-AI integration slowing your roadmap?
Chiplet and UCIe integration, embedded firmware, and edge-AI deployment each carry their own risk. We bring proven IP and software teams that have shipped it, so integration stops being the long pole on your schedule.
L4 Verification Is verification the bottleneck on your critical path?
Simulation samples; it can't prove a bug isn't there. Formal verification at enterprise scale gives you exhaustive proof on the blocks that matter — and the same rigor extends to RF and microwave design and test.
L5–6 Yield & orchestration Losing margin to yield surprises, or drowning in disconnected tools?
Yield data sits in the fab, design sits upstream, and nobody connects them. We close that loop with yield analytics, enterprise AI, and the compute to run it — turning the lifecycle into something you can actually orchestrate.
L1–L6 The cost of the stack, in one place Could you tell your CFO what your EDA tools actually cost, today?
License servers, vendor contracts and IP consumption live in separate systems, so spend stays invisible until the renewal bill lands — and nobody can connect it back to the design work driving it. We close that gap with a financial-control layer that sits across the whole stack, not just one part of it.
Twelve partners, one lifecycle — ordered intent (L1) to orchestration (L6). Open any one for the short version, then book a session or visit their site.
L1 Jama Software — live requirements traceability Requirements & traceability
The de facto requirements-management solution across the global semiconductor industry. Jama Connect keeps requirements, tests and design linked in real time — built for functional safety and audit.
L1 Glide — lifecycle data management Engineering data, end to end
A single, traceable source of truth for engineering data across the whole program lifecycle, so nothing gets lost between teams and tools.
L2 Rise Design Automation — AI-enabled HLS Architecture & synthesis
High-level synthesis that compresses the path from algorithm to optimized RTL, so architecture exploration takes days instead of months.
L2 MachineWare — high-performance virtual prototyping Pre-silicon software bring-up
Virtual platforms fast enough to boot and debug real software long before silicon arrives — so software stops waiting on hardware.
L3 InPsy — IP for high-performance chiplets IP & chiplets
IP engineered for chiplet and UCIe-class systems, where integration risk is highest and getting the interconnect right is everything.
L3 CraftifAI — embedded, IoT & edge-AI software Firmware & edge deployment
Firmware and edge-AI deployment across MCU, IoT and FPGA targets — the software muscle to actually ship what you've designed.
L3 ModelCat — automated AI model development AI model dev & optimization
Automated development and optimization of AI models for your silicon targets — getting models from prototype to production-ready faster.
L4 Axiomise — formal verification at enterprise scale Exhaustive proof, not sampling
Exhaustive, mathematical proof on the blocks that matter — not sampled simulation. Find the bugs simulation will never reach, sooner.
L4 Quaxys — RF & microwave design + cloud test RF & test
End-to-end RF and microwave design with a cloud-based test platform — closing the slow, fragmented loop between design and measurement.
L5 YieldWerx — yield analytics & manufacturing intelligence Yield & manufacturing
Turns test and yield data into action, connecting the fab back to design so margin surprises become signals you can act on.
L6 Softweb Solutions — enterprise AI, cloud & transformation Enterprise AI & orchestration
Enterprise AI and cloud — agent orchestration, intelligence layers, IoT and vision — to scale the whole lifecycle across the organization.
L6 Tuple Technologies — build, run & scale compute Compute & scale
The compute and AI-workload backbone behind the rest of the stack — build, run and scale your engineering and AI workloads without the infrastructure headache.
L1–L6 Veratum — DesignLedger, the financial-control layer EDA spend, finally visible
License servers, vendor contracts and IP consumption all live in different systems, so nobody — including the CFO — can see what design tools actually cost until the renewal bill lands. DesignLedger reconciles it into one auditable set of books, sitting across the whole EDA 3.0 stack rather than any single layer.
Who you'll be meeting
Seven people on the floor, no slideware ambush.
Simon Bennett
Former Synopsys CAE & operations director and Intel IP/EDA veteran. Architect of the EDA 3.0 thesis and co-author of The Connector's Playbook. Simon gives the EDA 3.0 overview.
John Simmons
EDA and IP veteran and co-author of the three-book series. The connector who knows the industry and opens the right doors to the right people.
Brandon Meredith
Runs partner solutions and live POCs on the floor — the person to grab for a hands-on look at any partner in the stack.
Sudeep Mehta
30+ years in enterprise IT, including seven years as Qualcomm's Senior Director of Engineering IT, where he led IP lifecycle management and cloud transformation programs. Sudeep is the one to talk to about IP protection, governance, and digital transformation at scale.
Fred Roberts
Nearly two decades at Synopsys spanning security engineering, quality, and CAE, with an ASIC/RTL verification background underneath it all. Fred partners with engineering teams across architecture, design, verification, and yield — bring him the hard technical questions.
Mark Milton
Built AiT's lead-gen engine and pipeline architecture from the ground up, owning HubSpot and ZoomInfo data integrity end-to-end. If you want a clean follow-up booked after DAC, Mark's making it happen.
Ashley Peti
Keeps partner operations — and DAC 2026 logistics — running without a hitch. Ashley's the go-to for anything scheduling, badges, or booth-related.
Making it all come together
You won't see them at the booth. You'd feel it if they weren't working.
Karen Shields
Six years at PayPal as Chief of Staff and Director of Enterprise Program Management, before that nearly two decades at eBay running mobile PM, QE, and engineering-operations teams. Karen is the reason AiT runs as one organization instead of a set of disconnected efforts — for DAC specifically, that's the booth staffing roster, the schedule, and the hundred small decisions nobody else has to think about.
Craig Raether
Built out AiT's HubSpot workflows and go-to-market sales process, drawing on a sales career that includes five years running enterprise territory at Oracle. Craig is the one making sure every conversation you have at DAC actually turns into a tracked, followed-up opportunity.
Tony Edwards
San Jose State design student who joined AiT full-time this summer. Tony designed the new AiT brand mark, the booth signage, and The Long Line, Series 1 — the trading cards you'll be walking away with.
Something else on your mind?
Tell us what you'd like to cover.
Not sure which session fits, or after something that isn't on the menu? Give us the gist and we'll line up the right people for your 1:1 at DAC — or a remote Teams slot if you're not in Long Beach.
Where to find us