AiT Partner · UCIe & Chiplet Interconnect IP
UCIe is standardized.
The IP that carries it is not.
Two UCIe blocks on the same process node can behave nothing alike once real packages, thermals and workloads set in. InPsy guarantees the link that everything else now depends on.
The moment confidence gets tested
Early in the program, the interconnect looks like a checkbox
Teams pick an IP provider, agree on bandwidth, latency and power assumptions, and move on. Then the system reality evolves. Packaging constraints shift, thermal budgets tighten, routing complexity grows — and the question quietly changes from whether the design works to whether the link behaves predictably under real system pressure.
The conversation shifts from “Does it support UCIe?” to “How much confidence does this give us when the system gets complicated?”
Slice quality ≠ system quality
A component that passes standalone can still miss once it lands in your ASIC and package. The margin that survives real routing and thermal is what actually ships.
The validation falls on you
Component-only vendors hand off implementation, packaging, SI/PI and design verification to the system team — exactly when schedule margin has disappeared.
Interconnect becomes a risk variable
More chiplets, more heterogeneous tiles, more aggressive targets. The die-to-die fabric stops being plumbing and becomes a first-order, system-level risk.
From the Watchtower
Why the interconnect is suddenly on the critical path
The center of gravity in a modern system has moved off the die and onto the package. When the meaningful unit is a system assembled from tiles, advantage is won or lost in how those tiles talk to each other. Three briefs we’ve written this year trace the shift.
Where UCIe Assumptions Get Stress-Tested
Why the interconnect stops being a specification exercise and becomes a system-level risk variable as chiplet designs scale.
Read the brief →Diamond Rapids: The CPU Becomes the Control Plane
Intel’s server roadmap reads like a public statement that the system now lives on the package — which puts UCIe on the critical path.
Read the brief →Chiplets and EDA
As EDA ecosystems tighten, fragmentation moves up the stack — and demand grows for neutral, cross-vendor capability at the interconnect boundary.
Read the brief →Where InPsy changes the outcome
A full ownership guarantee, not a component drop
InPsy takes end-to-end ownership of device-to-device quality — guaranteeing that your D2D link operates as proposed inside your ASIC and your package, not just on a datasheet.
The whole block, not the slice
Implementation of multiple UCIe blocks plus PLL, clock tree and glue logic — delivered with IP- and package-level SI/PI reports and full design-verification. Where other vendors hand off the hard integration, InPsy owns it.
First, repeatedly
First to silicon-proven UCIe at 16G (2022) and 32G (2023), plus 64G, 3D face-to-face SoIC and SoW-X. First to mass production on a Tier-1 US flagship AI accelerator, with 15+ UCIe programs projected to reach MP through 2029.
Bit error rate reachable in silicon — outperforming the UCIe 3.0 standard. Energy efficiency under 0.2 pJ/bit for UCIe-A, beating the specification by 50%+.
Tailored to your product
Bandwidth, beachfront-vs-depth-vs-reach, power budget, metal stack and package type tuned to your design — with an embedded MCU enabling firmware-based revisions after tape-out.
Fixed Tx / Rx per lane
The conventional approach: each lane is dedicated to one direction, decided at design time. Predictable, but it spends beachfront and power to reach a bandwidth target.
InPsy SBD — every lane transmits and receives at once
Simultaneous Bi-Directional architecture lets the clock tree and PLL run at half the frequency for the same throughput — three breakthroughs in one macro:
The partner
InPsytech — the Egis Group silicon-IP subsidiary
A high-speed interconnect specialist pioneering high-complexity silicon IP on the most advanced process nodes, with value-added integration and SI/PI services that carry customers from evaluation to tape-out.
Ecosystem: ARM Total Design · Samsung SAFE™ IP Alliance · Intel Foundry Accelerator IP Alliance · recognized for outstanding partnership by a leading AI-accelerator program.
The AiT play
Where InPsy sits in the EDA 3.0 lifecycle
AiT’s thesis is that as silicon disaggregates, the bottleneck stops being any single tool and becomes orchestration across the lifecycle — from intent to yield. InPsy anchors the architecture and physical-interconnect layers, where die-to-die decisions get locked in.
The link everything depends on shouldn’t be the thing you find out about at tape-out
If your team is working through UCIe partitioning or evaluating interconnect IP, that’s the conversation. Thirty minutes, no slides required.
Book a die-to-die briefing