--- title: inpsy description: Inpsy is the new leader in UCIe IP image: https://www.ai-techsales.com/hubfs/inpsy-hero.png --- The moment confidence gets tested ## Early in the program, the interconnect looks like a checkbox Teams pick an IP provider, agree on bandwidth, latency and power assumptions, and move on. Then the system reality evolves. Packaging constraints shift, thermal budgets tighten, routing complexity grows — and the question quietly changes from whether the design works to whether the link behaves predictably under real system pressure. The conversation shifts from **“Does it support UCIe?”** to **“How much confidence does this give us when the system gets complicated?”** 01 ### Slice quality ≠ system quality A component that passes standalone can still miss once it lands in your ASIC and package. The margin that survives real routing and thermal is what actually ships. 02 ### The validation falls on you Component-only vendors hand off implementation, packaging, SI/PI and design verification to the system team — exactly when schedule margin has disappeared. 03 ### Interconnect becomes a risk variable More chiplets, more heterogeneous tiles, more aggressive targets. The die-to-die fabric stops being plumbing and becomes a first-order, system-level risk. From the Watchtower ## Why the interconnect is suddenly on the critical path The center of gravity in a modern system has moved off the die and onto the package. When the meaningful unit is a system assembled from tiles, advantage is won or lost in how those tiles talk to each other. Three briefs we’ve written this year trace the shift. ### [UCIe · Advanced Packaging Where UCIe Assumptions Get Stress-Tested Why the interconnect stops being a specification exercise and becomes a system-level risk variable as chiplet designs scale. Read the brief →](https://www.ai-techsales.com/ai-tech-sales-blog/where-ucie-assumptions-get-stress-tested?hsLang=en) ### [Chiplets · UCIe Diamond Rapids: The CPU Becomes the Control Plane Intel’s server roadmap reads like a public statement that the system now lives on the package — which puts UCIe on the critical path. Read the brief →](https://www.ai-techsales.com/ai-tech-sales-blog/diamond-rapids-the-cpu-becomes-the-control-plane?hsLang=en) ### [Chiplets · EDA 3.0 Chiplets and EDA As EDA ecosystems tighten, fragmentation moves up the stack — and demand grows for neutral, cross-vendor capability at the interconnect boundary. Read the brief →](https://www.ai-techsales.com/ai-tech-sales-blog/chiplets-and-eda?hsLang=en) Where InPsy changes the outcome ## A full ownership guarantee, not a component drop InPsy takes end-to-end ownership of device-to-device quality — guaranteeing that your D2D link operates as proposed inside your ASIC and your package, not just on a datasheet. END-TO-END D2D GUARANTEE ### The whole block, not the slice Implementation of multiple UCIe blocks plus PLL, clock tree and glue logic — delivered with IP- and package-level SI/PI reports and full design-verification. Where other vendors hand off the hard integration, InPsy owns it. SILICON-PROVEN TRACK RECORD ### First, repeatedly First to silicon-proven UCIe at 16G (2022) and 32G (2023), plus 64G, 3D face-to-face SoIC and SoW-X. First to mass production on a Tier-1 US flagship AI accelerator, with 15+ UCIe programs projected to reach MP through 2029. PERFORMANCE HEADROOM 1E-23 Bit error rate reachable in silicon — outperforming the UCIe 3.0 standard. Energy efficiency under 0.2 pJ/bit for UCIe-A, beating the specification by 50%+. CUSTOM, NOT CATALOG ### Tailored to your product Bandwidth, beachfront-vs-depth-vs-reach, power budget, metal stack and package type tuned to your design — with an embedded MCU enabling firmware-based revisions after tape-out. Unidirectional Simultaneous Bi-Directional #### Fixed Tx / Rx per lane The conventional approach: each lane is dedicated to one direction, decided at design time. Predictable, but it spends beachfront and power to reach a bandwidth target. #### InPsy SBD — every lane transmits and receives at once Simultaneous Bi-Directional architecture lets the clock tree and PLL run at half the frequency for the same throughput — three breakthroughs in one macro: **+100%**bandwidth across the same beachfront **−50%**beachfront for the same bandwidth **−40–50%**power — 2× bandwidth at only 1.5× power The partner ## InPsytech — the Egis Group silicon-IP subsidiary A high-speed interconnect specialist pioneering high-complexity silicon IP on the most advanced process nodes, with value-added integration and SI/PI services that carry customers from evaluation to tape-out. Core technology UCIe PHY + Controller, high-speed D2D & data-transfer IP Process reach 2 / 3 / 4 / 5 / 6 / 7 / 12 / 22nm across leading foundries Foundries TSMC · Samsung · Intel · UMC Team ~153 engineers · Hsinchu, Taiwan **Ecosystem:** ARM Total Design · Samsung SAFE™ IP Alliance · Intel Foundry Accelerator IP Alliance  ·  recognized for outstanding partnership by a leading AI-accelerator program. The AiT play ## Where InPsy sits in the EDA 3.0 lifecycle AiT’s thesis is that as silicon disaggregates, the bottleneck stops being any single tool and becomes orchestration across the lifecycle — from intent to yield. InPsy anchors the architecture and physical-interconnect layers, where die-to-die decisions get locked in. L1 **Intent & Requirements** L2 **Architecture & Modeling** — chiplet partitioning, D2D bandwidth & reach tradeoffsInPsy L3 **RTL, Firmware & Physical IP** — UCIe PHY + Controller, SI/PI, packageInPsy L4 **Verification** L5 **Yield & Physical** L6 **AI Orchestration** [Read the full EDA 3.0 thesis →](https://www.ai-techsales.com/what-is-EDA-3.0?hsLang=en) ## The link everything depends on shouldn’t be the thing you find out about at tape-out If your team is working through UCIe partitioning or evaluating interconnect IP, that’s the conversation. Thirty minutes, no slides required. [Book a die-to-die briefing](https://www.ai-techsales.com/contact?hsLang=en) AiT represents InPsytech across North America.  ·  [The Watchtower Brief](https://www.ai-techsales.com/ai-tech-sales-blog?hsLang=en)  ·  [inpsy.com](https://www.inpsy.com)  ·  © 2026 AI Tech Sales