Every chip design tool stops at tape-out. The part goes to the fab, and the arrow ends. Telemetry is what sends the arrow back: the on-chip signal that tells you what the silicon actually did. It is also the missing half of EDA 3.0.

The arrow that stops at tape-out

Everything before tape-out is a model. Simulation, timing, power, all of it a prediction of how the chip should behave. When the first parts come back from the fab, those predictions meet physics for the first time. In the tool-centric world I came up in at Synopsys, the flow ran in one direction: intent, design, verification, tape-out, silicon. What the silicon then did, in the fab and out in the field, almost never found its way back to the people who designed it.

The loop was open. That open loop is the quiet inefficiency at the heart of what I have called EDA 2.0. We got very good at pushing work leftward into simulation and formal, and we left the return path undrawn.

What telemetry actually is

Telemetry is silicon that reports on itself. It rests on three families of on-chip instrumentation. On-die sensors read the physical state: temperature, voltage droop, current, process corner, and aging. Performance counters tally what the logic is doing, cycle by cycle, from instructions retired to cache misses, memory bandwidth, and pipeline stalls. And a debug and trace fabric exposes internal signals and program flow in real time, without stopping the part. Together they are the observability layer of everything that happens after first silicon.

None of this is new to a post-silicon validation engineer. What is new is where the data now has to travel.

From bench aid to fleet requirement

For a long time telemetry was a bring-up tool, something you used to root-cause a failure on the bench in the first weeks with a chip. That has changed. Modern data-center parts are power-limited, so the entire value proposition is tokens per watt, and you cannot credibly claim an efficiency number that nothing on the chip measures. Qualcomm's new Dragonfly data-center portfolio is built around exactly this logic, with performance-per-watt as the headline lever.

Now layer on the buyers. When your customers are hyperscalers running millions of parts, telemetry stops being a debug aid and becomes a shipped feature. Those operators have been living with silent data corruption since the now-famous studies on the cores that do not count, where a handful of chips miscompute intermittently with no error flag at all. At fleet scale, a rare defect becomes an everyday certainty, and the only defense is continuous, in-field observability, per-core health signals, and the ability to route work away from a suspect part before it drops a job.

Closing the loop

Here is the shift in framing. Pre-silicon verification is shift-left: catch problems early, in simulation and formal. Telemetry is the shift-right counterpart: learn from real silicon as it actually runs. EDA 3.0, the thesis we have been building at AiT, is fundamentally about fusing those two halves into a single feedback loop.

Feed real-silicon behaviour back up the stack and design stops being a one-way street. The measured result at the yield and physical layer becomes feedback to intent (did we hit the target we specified?), to modeling (were the power and thermal assumptions right?), and to verification (every field escape is a coverage gap that tells the next cycle exactly where to look). Telemetry is the data source that makes that loop physically possible. Without it, the return arrow in the diagram above is just wishful thinking.

You cannot orchestrate a lifecycle you cannot measure. Telemetry is where the measuring happens.

The unclaimed high ground

The incumbents, Synopsys, Cadence, and Siemens, together hold roughly three-quarters of the EDA market, and they are genuinely strong at tool-level AI. What they lack is an intent layer at the top and a yield connection at the bottom. Their tools remain largely siloed from what the manufactured part does in the world. Telemetry is precisely the connective tissue across that gap, the signal that carries outcomes back to intent.

Whoever owns that loop, rather than any single tool inside it, owns the orchestration position. That position is still unclaimed. It is the same argument I made in EDA Is Entering Its Third Era and The Validation Crisis in AI Silicon, now with the return path drawn in.

Simon Bennett is Principal Solutions Consultant and Co-Founder of AI Tech Sales, and a former Synopsys and Intel IP and EDA veteran. The Watchtower Brief is the firm's editorial series on the changing shape of the semiconductor lifecycle.