CraftifAI Embedded & Firmware

The Firmware Under the Fabric: PCIe 7.0, CXL 4.0 and the Bring-Up Gap

Simon Bennett

October 4, 2026

WATCHTOWER BRIEF · EMBEDDED & FIRMWARE

AiT × CRAFTIFAI · TECHNICAL NOTE

Every interconnect generation doubles the wire. The firmware that trains the link, keeps it healthy and explains its failures has to keep pace, and that is now where interconnect schedules are decided.

The wire keeps doubling

PCI-SIG finalized PCIe 7.0 in mid-2025: 128 GT/s per lane, up to 512 GB/s bidirectional across an x16 link, carried on the same PAM4 signaling and FLIT-based encoding that PCIe 6.0 introduced, and backward compatible with every earlier generation. The CXL Consortium followed in November 2025 with CXL 4.0, built on the PCIe 7.0 physical layer, doubling bandwidth again and stretching memory pooling across multiple racks. PCIe 8.0 is already in draft, aimed at 2028.

Since PCIe 4.0 the cadence has settled at roughly one new generation every two and a half years. The first silicon to adopt each one is the same every time: AI accelerators, switches and retimers, high-performance storage, and memory expansion. Those are also the products where a link that will not train, or a fabric that cannot report its own health, stops a platform from shipping.

Where the firmware actually lives

Bandwidth is specified in the PHY. Almost everything that makes a PCIe or CXL device usable in a real system is implemented in firmware running on the embedded cores inside the controller, switch, retimer or memory expander:

LINK BRING-UP

Training orchestration, equalization presets and per-board tuning, so the link comes up at full rate on every reference platform, not just the evaluation board.

RAS AND ERRORS

Advanced error reporting, FLIT retry behavior, poison handling and the policies that decide when a degraded link is tolerated and when it is taken down.

DEVICE MANAGEMENT

CXL mailbox commands, CDAT tables, component state and the telemetry a fabric manager needs to place memory and workloads sensibly.

SECURITY

SPDM attestation, IDE link encryption and TDISP device assignment, now expected rather than optional in data center platforms.

MANAGEABILITY

MCTP and PLDM paths to the BMC, firmware update, and the sideband plumbing that operations teams depend on long after launch.

Why this becomes the schedule

Each specification generation touches most of those layers. Each product family multiplies them: lane widths, port counts, retimer and switch variants, customer-specific reference designs. The validation matrix grows with every combination, while the firmware team that owns it is usually far smaller than the RTL team it serves.

Hardware teams have simulation, emulation and virtual platforms to get ahead of silicon. Firmware too often starts from the previous generation's code, ported by hand once the new hardware description settles. Much of that effort goes into plumbing that looks almost the same from one variant to the next, and it sits squarely on the critical path between first silicon and a platform customers can qualify.

THE BRING-UP GAP

Silicon arrives on schedule. The link has to train across every platform configuration, report its own health and pass security attestation before anyone can ship it, and all of that is firmware.

What generated, validated firmware changes

CraftifAI built FirmGen, part of its CraftifAI Orbit platform, for exactly this kind of work. It generates firmware from a hardware description and requirements, then builds, flashes and validates it on the target in a closed loop, with vendor SDKs already indexed. It deploys on-prem as well as in the cloud, which matters when the code in question is a controller roadmap nobody wants leaving the building.

Applied to interconnect silicon, the useful effects are practical rather than dramatic:

Each new controller, switch or retimer variant starts from a working, reviewable firmware baseline instead of a port of the last generation.

When the specification moves, the management, telemetry and manageability layers can be regenerated from the updated description and validated again on target, rather than rewritten.

The engineers who know the link best spend their time on equalization tuning, RAS policy and security design, the parts that actually differentiate the product.

Three questions for interconnect teams

How many firmware images does one product family carry per specification generation, once lane widths, port counts and customer reference designs are counted?

How long does it take from first silicon to a link that trains at full rate on every reference platform you support?

When CXL 4.0 features land on your roadmap, which firmware layers change, and who rewrites them?

If those questions land close to home, AiT represents CraftifAI in North America and can arrange a technical session with the CraftifAI team. Learn more at ai-techsales.com/craftifai or reach us directly at simon@ai-techsales.com.

SOURCES: PCI-SIG, PCI Express 7.0 specification release (June 2025), pcisig.com. CXL Consortium, Compute Express Link 4.0 specification release (November 2025), computeexpresslink.org. Product capabilities described per CraftifAI.